ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
Preliminary Technical Data
SPI Interface—Slave
Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Min
Timing Requirements
tSPICLKS
Serial Clock Cycle
TBD
tSPICHS
Serial Clock High Period
TBD
tSPICLS
Serial Clock Low Period
TBD
tSDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
TBD
CPHASE = 1
TBD
tHDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
TBD
tSSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time)
TBD
tHSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
TBD
tSDPPW
SPIDS Deassertion Pulse Width (CPHASE=0)
TBD
Switching Characteristics
tDSOE
tDSDHI
tDDSPIDS
tHDSPIDS
tDSOV
SPIDS Assertion to Data Out Active
TBD
SPIDS Deassertion to Data High Impedance
TBD
SPICLK Edge to Data Out Valid (Data Out Delay Time)
TBD
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
TBD
SPIDS Assertion to Data Out Valid (CPHAS E = 0)
TBD
Max
Unit
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
tSDSCO
SPICLK
(CP = 1)
(INPUT)
tDSOE
tSPIC HS
tSPICLS
tDDSPIDS
tSPICLS
tSPICHS
tSPICLKS
tHDS
tDDSPIDS
MISO
(OUTPUT)
CPHASE = 1
MOSI
(INPUT)
tSSPIDS
MISO
(OUTPUT) t D S OV
CPHASE = 0
MSB
MSB
MSB VALID
tDDSPIDS
MOSI
(INPUT)
MSB VALID
tSSPIDS
LSB
tHSPIDS
LSB VALID
tHDSPIDS
LSB
tSSPIDS
tHSPIDS
LSB VALID
tSDPPW
tDSDHI
tHDSPIDS
tDSDHI
Figure 35. SPI Slave Timing
Rev. PrB | Page 46 of 56 | November 2008
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