ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-21469/ADSP-21469W
SPI Interface—Master
The ADSP-21469 contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 42 and Table 43 applies to both.
Table 42. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Min
Timing Requirements
tSSPIDM
Data Input Valid To SPICLK Edge (Data Input Setup Time)
TBD
tHSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid
TBD
Switching Characteristics
tSPICLKM
Serial Clock Cycle
TBD
tSPICHM
Serial Clock High Period
TBD
tSPICLM
Serial Clock Low Period
TBD
tDDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
TBD
tHDSPIDM
tSDSCIM
tHDSM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
TBD
FLAG3–0IN (SPI device select) Low to First SPICLK Edge
TBD
Last SPICLK Edge to FLAG3–0IN High
TBD
tSPITDM
Sequential Transfer Delay
TBD
Max
Unit
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
TBD
ns
TBD
ns
TBD
ns
TBD
ns
FLAG3-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
MOSI
(OUTPUT)
CPHASE = 1
MISO
(INPUT)
tSDSCIM tSPICHM tSPICLM
tSPICLM
tSPICHM
tD DS P I DM
MSB
tSSPIDM
MSB
VALID
tHSPIDM
MOSI
(OUTPUT)
CPHASE = 0
tSSPIDM
MISO
(INPUT)
MSB
tHSPIDM
MSB
VALID
tDDSPIDM
tSPICLKM
tHDSM
tSPITDM
t HDSPIDM
tSSPIDM
tHDSPIDM
LSB
LSB
VALID
tHSPIDM
LSB
LSB
VALID
Figure 34. SPI Master Timing
Rev. PrB | Page 45 of 56 | November 2008
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