ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-21469/ADSP-21469W
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 39. Input signals (SCLK, FS, SDATA) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 39. S/PDIF Transmitter Input Data Timing
Parameter
Min
Max
Unit
Timing Requirements
tSISFS1
FS Setup Before SCLK Rising Edge
tSIHFS1
FS Hold After SCLK Rising Edge
tSISD1
SData Setup Before SCLK Rising Edge
tSIHD1
SData Hold After SCLK Rising Edge
tSITXCLKW
Transmit Clock Width
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
tSITXCLK
tSISCLKW
Transmit Clock Period
Clock Width
TBD
TBD
ns
TBD
TBD
ns
tSISCLK
Clock Period
TBD
TBD
ns
1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
DAI_P20-1
(TXCLK)
tSITXCLKW
tSITXCLK
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
tSISCLKW
tSISCLK
tSISFS
tSISD
Figure 32. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 40. Over Sampling Clock (TxCLK) Switching Characteristics
Parameter
Min
TxCLK Frequency for TxCLK = 384 × FS
TBD
TxCLK Frequency for TxCLK = 256 × FS
TBD
Frame Rate
TBD
tSIHFS
tSIHD
Max
TBD
TBD
TBD
Unit
MHz
MHz
kHz
Rev. PrB | Page 43 of 56 | November 2008
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