LRS1302 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1302' PDF : 61 Pages View PDF
SHARP
LRS13023
10
~Individual block locking uses a combination of bits,
‘sixteen block lock-bits and a master lock-bit, to lock
land unlock blocks. Block lock-bits gate block erase and
‘byte write operations, while the master lock-bit gates
~block lock-bit modification. Lock-bit configuration
loperations (Set Block Lock-Bit, Set Master Lock-Bit,
and Clear Block Lock-Bits commands) set and cleared
lock-bits.
The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation is
finished.
The access time is 130 ns (tAvQv) over the commercial
temperature range (-40°C to +BS’C) and V,, supply
voltage range of 2.7V-3.6V.
The Automatic Power Savings (AI%) feature
substantially reduces active current when the device is
in static mode (addresses not switching).
When a and RF pins are at V,,, the I,, CMOS
standby mode is enabled. When the RP pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection
during reset. A reset time (tPHqv) is required from RP
switching high until outputs are valid. Likewise, the
device has a wake time (tpHEL) from m-high until
writes to the CUI are recognized. With RP at GND, the
WSM is reset and the status register is cleared.
4 x:
occcdc.r .
.
16
64KByle
BlOCb
Figure 1. Block Diagram
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