LRS1302 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1302' PDF : 61 Pages View PDF
SHARP
LRS13023
18
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CLJI
remains in read status register mode until a new
command is issued.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to “1”. Also, reliable block erasure
can only occur when Vcc=VccI and V,=V,,,. In the
absence of this high voltage, block contents are
protected against erasure. If block erase is attempted
while Vppflppm, SR.3 and SR5 will be set to “1”.
Successful block erase requires that the corresponding
block lock-bit be cleared or, if set, that m=V,. If
block erase is attempted when the corresponding
block lock-bit is set and m=V,,, SR.1 and SR5 wi.lI be
set to “1”. Block erase operations with V,<pcV,
produce spurious results and should not be attempted.
4.6 Byte Write Command
Byte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or alternate
10H) is written, followed by a second write that
specifies the address and data (latched on the rising
edge of WE). The WSM then takes over, controlling the
byte write and write verify algorithms internally. After
the byte write sequence is written, the device
automatically outputs status register data when read
[see Figure 5). The CPU can detect the completion of
the byte write event by analyzing status register bit
3R.7.
When byte write is complete, status register bit SR.4
should be checked. If byte write error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1% that do not
juccessfully write to “0”s. The GUI remains in read
jtatus register mode until it receives another
:ommand.
&liable byte writes can only occur when V,c=VccI
md Vpp=Vppw In the absence of this high voltage,
nemory contents are protected against byte writes. If
>yte write is attempted while VpplVppm, status
register bits SR3 and SR4 will be set to “1”. Successful
byte write requires that the corresponding block
lock-bit be cleared or, if set, that i@=V,. If byte write
is attempt-ed when the corresponding block lock-bit is
set and RP=V,,, SR.l and SR4 will be set to “1”. Byte
write operations with VI,<m<V,,
produce spurious
results and should not be attempted.
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block-erase
interruption to read or byte-write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests
that the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device
outputs status register data when read after the Block
Erase Suspend command is written. Polling status
register bits SR.7 and SR.6 can determine when the
block erase operation has been suspended (both will
be set to “1”). Specification tw- defines the block
erase suspend latency. I I
.%
At this point, a Read Arraycomman d can be written to
read data from blocks other than that which is
suspended. A Byte:Write comman d sequence can also
be issued during erase suspend to program data. in
other blocks. Using the Byte Write Suspend command
(see Section 4.81,. a..byte write operation can also. be
suspended. During-a byte write operation with block
erase suspended, status registerbit SR7 will return to
“0” . However, SR.6 will remain “1” to indicate block
erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is
written to the flash memory, the WSM will continue
the block erase process. Status register bits SR.6 and
SR7 will automatically clear . After the Erase Resume
command is written, the device automatically outputs
status register data when read (see Figure 6). VP, must
remain at VP,, (the same Vpp level used for block
erase) while block erase is suspended. m must also
remain at VI, or V, (the same m level used for
block erase). Block erase cannot resume until byte
write operations initiated during block erase suspend
have completed.
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