LRS1302 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1302' PDF : 61 Pages View PDF
SHARP
LRS13023
11
Svm
f40-419
I/O&O~
-
CE
Rp
O_.E_-
WE
bP
Vcc
GND
rote: V,-,
Type
INPUT
INPUT/
OUTPUT
INPUT
INPUT
INPUT
INPUT
SUPPLY
SUPPLY
SUPPLY
,P, n, m
Table 2. Pin Descriptions
Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. a-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. m-high enables normal operation. When driven low, p inhibits
write operations which provides data protection during power transitions. Exit from
deep power-down sets the device to read array mode. Ris at V,, enables setting of the
mast-er lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP=V,,, overrides block lock-bits thereby enabling block erase and byte write
operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with V,,<RI’cV&
produce spurious results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE pulse.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION
POWER SUPPLY: For
erasing array blocks, writing bytes, or configuring lock-bits. With VPP5VPPLK, memory
contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid VP, (see DC Characteristics) produce spurious results and should not be
attempted.
DEVICE POWER SUPPLYDo not float any power pins. With VCCIVLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid Vcc voltage (see
DC Characteristics) produce spurious results and should not be attempted. Block erase,
byte write and lock-bit configuration operations with V,,<3.OV are not supported.
GROUND: Do not float any ground pins.
and WE mean F-V,,, F-V,,, F-a, Fa and F-WE.
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