LRS1302 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1302' PDF : 61 Pages View PDF
SHARI=
LRS13023
12
2 PRINCIPLES OF OPERATION
The LRS1302 SmartVoltage Flash memory includes an
on-chip WSM to manage block erase, byte write, and
lock-bit configuration functions. It allows for: 100%
TTL-level control inputs, fixed power supplies during
block erasure, byte write, and lock-bit configuration,
and minimal processor overhead with RAM-Like
interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the VP, voltage. High
voltage on V,, enables successful block erasure, byte
writing, and lock-bit configuration. All functions
associated with altering memory contents-block erase,
byte write, Lock-bit configuration, status, and
identifier codes-are accessed via the CUI and verified
through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, byte write, and
lock-bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification, and margining of data. Addresses
and data are internally latch during write cycles.
Writing the appropriate command outputs array data,
accesses the identifier codes, or outputs status register
data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and
executed from system RAM during flash memory
updates. After successful completion, reads are again
possible via the Read Array command. Block erase
suspend allows system software to suspend a block
erase to read or write data from any other block. Byte
write suspend allows system software to suspend a
byte write to read data from any other flash memory
array location.
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Figure 2. Memory Map
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V,, power supply switchable
(available only when memory block erases, byte
writes, or lock-bit configurations are required) or
hardwired to V,,,. The device accommodates either
design practice and encourages optimization of the
processor-memory interface.
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