LRS1302 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1302' PDF : 61 Pages View PDF
SHARP
LRS13023
.
17
:.l Read Array Command
Jpon initial device power-up and after exit from deep
jowerdown mode, the device defaults to read array
node. This operation is also initiated by writing the
lead Array command. The device remains enabled for
eads until another command is written. Once the
nternal WSM has started a block erase, byte write or
sck-bit configuration, the device will not recognize
he Read Array command until the WSM completes its
lperation unless the WSM is suspended via an Erase
luspend or Byte Write Suspend command. The Read
bray command functions independently of the VP,
poltage and m can be V,, or V,,.
,.2 Read Identifier Codes Command
‘he identifier code operation is initiated by writing the
Lead Identifier Codes command. Following the
ommand write, read cycles from addresses shown in
‘igure 3 retrieve the manufacturer, device, block lock
onfigura tion and master lock configuration codes (see
‘able 5 for identifier code values). To terminate the
Nperation, write another valid command. Like the
Lead Array command, the Read Identifier Codes
omm-and functions independently of the VP, voltage
nd RP can be V,, or V,,. Following the Read
dentifier Codes command, the following information
an be read:
Table 5. Identifier Codes
Block Lock Configuration
.Block is Unlocked
*Block is Locked
-Reserved for Future Use
Master Lock Configuration
SDevice is Unlocked
,Device is Locked
,Reserved for Future Use
IOTE:
. X selects the specific block lock configuration code
to be read. See Figure’3 for the device identifier
code memory map.
4.3 Read Status Register Command
The status register may be read to determine when a
block erase, byte write, or, lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing the
Read Status Register command. After writing this
command, all subsequent read operations output data
from the status register until another valid command
is written. The status register contents are latched on
the falling edge of OE or CE, whichever occurs. OE or
iZ must toggle to V,, before further reads to update
the status register latch. The Read Status Register
command functions independently of the VP, voltage.
Rp can be V,, or V,,.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to
“1”s by the WSM and can only be reset by the Clear
Status Register command. These bits indicate various
failure conditions (see Table 7). By allowing system
software to reset these bits, several operations (such as
cumulatively erasing or locking multiple blocks or
writing several bytes in sequence) may be performed.
The status register may be polled to determine if an
error occurre during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently
of the applied VP, Voltage. RP can be V,, or V,,.
This command is not functional during block erase or
byte write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first
written, followed by an block erase confirm. This
command sequence requires appropriate sequencing
and an address within the block to be erased (erase
changes all block data to FFH). Block preconditioning,
erase, and verify are handled internally by the WSM
(invisible to the system). After the two-cycle block
erase sequence is written, the device automatically
outputs status register data when read (see Figure 4).
The CPU can detect block erase completion by
analyzing status register bit SR.7.
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