LRS1302 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1302' PDF : 61 Pages View PDF
SHARI=
LRS13023
13
When VPPIVPPLK, memory contents cannot be altered.
The CUI, with two-step block erase, byte write, or
lock-bit configuration command sequences, provides
protection from unwanted operations even when high
voltage is applied to VP+. All write functions are
disabled when V,, is below the write lockout voltage
VLKO or when RP is at Vl,. The device’s block locking
capability provides additional protection from
inadvertent code or data alteration by gating erase and
byte write operations.
3 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash memory
:onform to standard microprocessor bus cycles.
3.1 Read
.c
Information can be read from any block, identifier
:odes, or status register independent of the VP,
voltage. RP can be at either Vl, or V,,.
The first task is to write the appropriate read mode
:ommand (Read Array, Read Identifier Codes, or Read
status Register) to the CUI. Upon initial device
Tower-up or after exit from deep power-down mode,
:he device automatically resets to read array mode.
Four control
:he component:
pins-C--Ed, icOtaEt,e
the
WE,
data flow
and m. CE
in and
and m
out of
must
>e driven active to obtain data at the outputs. m is the
device selection control, and when active enables the
ielected memory device. m is the data output
I/O&O,)
control and when active drives the
ielected memory data onto the I/O bus. WE must be
it VI, and m must be at V,, or V,,. Figure 12
llustrates a read cycle.
1.2 Output Disable
Mith 0lY at a logic-high level (Vt,), the device outputs
Ire disabled. Output pins I/0,-1/0, are placed in a
high-impedance state.
3.3 Standby
n at a logic-high level (V,,) places the device in
standby mode which substantially reduces device
power consumption. I/O&O, outputs are placed in
a high-impedance state independent of OE. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation completes.
3.4 Deep Power-Down
i?Ij at V,, initiates the deep power-down mode.
In read modes, m-low deselects the memory, places
output drivers in a high-impedance state and turns off
all internal circuits. RP must be held low for a
minimum of 100 ns. Time tPHQv is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, byte write, or lock-bit
configuration modes, m-low will abort the operation.
Memory contents being altered are no longer valid; the
data may be partially erased or written. Time tpHWL is
required after Rp goes to logic-high (VI,) before
another command can be written.
As with any automated device, it is important to assert
Rp during system reset. When the system comes out of
reset, it expects to read from the flash memory.
Automated flash memories provide status information
when accessed during block erase, byte write, or
lock-bit configuration modes. If a CPU reset occurs
with no flash memory reset, proper CPU initialization
may not occur because the flash memory may be
providing status information instead of array data.
SHARP’s flash memories allow proper CPU
initialization following a system reset through the use
of the i?l? input. In this application, Rp is controlled by
the same m
signal that resets the system CPU.
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