MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 45: WRITE – without Auto Precharge
T0
T1
T2
T3
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
DQM
tCMS tCMH
ADDR
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
COLUMN m
DISABLE AUTO PRECHARGE
BANK
tDS tDH
tDS tDH
DQ
tRCD
tRAS
tRC
DIN m
DIN m + 1
T4
NOP
tDS tDH
DIN m + 2
T5
NOP
tDS tDH
DIN m + 3
T6
NOP
tWR2
T7
PRECHARGE
ALL BANKS
SINGLE BANK
BANK
T8
NOP
tRP
T9
ACTIVE
ROW
ROW
BANK
DON’T CARE
Notes:
1. For this example, BL = 4, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of fre-
quency.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
64
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