MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 48: Single WRITE – with Auto Precharge
T0
CLK
T1
tCK
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP3
T2
tCL
tCH
NOP3
DQM
tAS tAH
ADDR
ROW
tAS tAH
A10
BA0, BA1
ROW
tAS tAH
BANK
DQ
tRCD
tRAS
tRC
T3
T4
T5
NOP3
WRITE
NOP
tCMS tCMH
COLUMN m
ENABLE AUTO PRECHARGE
BANK
tDS tDH
DIN m
tWR
T6
NOP
T7
T8
T9
NOP
ACTIVE
NOP
ROW
ROW
BANK
tRP
DON’T CARE
Notes:
1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. WRITE command not allowed or tRAS would be violated.
See Table 11 on page 46.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
67
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