MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 47: Single WRITE – without Auto Precharge
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
NOP3
DQM
ADDR
tAS tAH
ROW
COLUMN m
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
DISABLE AUTO PRECHARGE
BANK
tDS tDH
DQ
DIN m
tRCD
tRAS
tRC
tWR2
T4
T5
T6
NOP3
PRECHARGE
NOP
ALL BANKS
SINGLE BANK
BANK
tRP
T7
ACTIVE
ROW
BANK
T8
NOP
DON’T CARE
Notes:
1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. PRECHARGE command not allowed or tRAS would be violated.
See Table 11 on page 46.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
66
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