SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.16 The EFM clock generator
The EFM clock generator will produce the recording clock based on one of three reference sources. There are five stages
to the function. The first selects the reference source using a multiplexer. The next stage is a digital PLL to up-multiply
the reference source. The source will determine the base frequency output by the PLL, whilst a position error signal is
used to alter the frequency so that the position error tends to zero. Next, an analog PLL is used to up-multiply the output
from the digital PLL. The output of the analog PLL is then multiplexed with an external source to allow the EFM clock
generator to be bypassed completely. Finally, a programmable divider is used to enable the clock output, XEFM, to be
doubled producing XEFM_2.
handbook, full pagewidth
W441
WCLK
Sysclk/192
XError
Fifo filling
Sysclk
Config Data
MUX
MUX
DIGITAL
PLL
ANALOG
PLL
MUX
PROGRAMMABLE
DIVIDER
XEFM
+
Kp
Ki
+
INTEGRATOR
MGR808
Fig.18 EFM PLL block diagram.
2000 Mar 21
54
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