SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.16.2 EFM CLOCK CONFIGURATION REGISTER 2 (EFMCLOCKCONF2)
Table 124 EFM Clock Configuration Register 2 (address 35H) - WRITE
7
FreqSrc.1
6
FreqSrc.0
5
PosSrc.1
4
PosSrc.0
3
DPLLMF.3
2
DPLLMF.2
1
DPLLMF.1
0
DPLLMF.0
Table 125 Description of EFMClockConf2 bits
BIT
SYMBOL
DESCRIPTION
7
FreqSrc.1 These 2 bits select the frequency source for the PLL; see Table 126.
6
FreqSrc.0
5
PosSrc.1 These 2 bits select the position source; see Table 127.
4
PosSrc.0
3
DPLLMF.3 These 4 bits select the multiplication factor for the PLL; see Table 128
2
DPLLMF.2
1
DPLLMF.1
0
DPLLMF.0
Table 126 Selection of PLL frequency source
FreqSrc.1
0
0
1
1
FreqSrc.0
0
1
0
1
FREQUENCY SOURCE
PLL locks to W441. Use this signal as frequency source to lock EFM frequency to disc
wobble.
PLL locks to WCLK. Use this signal if encoding must slave to the word clock of some
external I2S/EBU input.
PLL locks to sysclock/192
This setting is reserved.
Table 127 Selection of position source
PosSrc.1
0
1
1
X
PosSrc.0
0
0
1
X
POSITION SOURCE
No position error used.
Position source is XError<6:0>. Use this source if EFM clock is locked to ATIP carrier
(W441).
Position source is FifoFill<6:0>. Use this source is EFM clock is locked to WCLK signal.
All other combinations are reserved.
Table 128 Digital PLL multiplication factor
DPLLMF.3
0
0
0
0
0
1
1
DPLLMF.2
0
0
0
1
1
0
0
DPLLMF.1
0
0
1
0
1
0
1
DPLLMF.0
0
1
0
0
0
0
0
DIGITAL PLL MULTIPLICATION FACTOR
294
196
147
98
73.5
49
36.75
2000 Mar 21
56
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