SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.17 The Wobble processor
The Wobble processor is a critical part of the recording
process, and performs two main functions:
• To extract the ATIP data from the wobble signal
• To control the linear disc speed during recording.
The Wobble processor comprises four functions, a
front-end ADC, a digital PLL, the ATIP bit detector and the
ATIP data read interface.
7.17.1 THE WOBBLE ADC FUNCTION
This converts the ATIP signal (WIN) to the digital domain.
7.17.2 THE WOBBLE PLL
The PLL has a PI type loop filter. The bandwidth of the loop
and the integrator are programmable by the user. The user
can also read and write the PLL frequency, the write mode
is available to aid PLL lock-in. The block outputs a pulse
signal at 44.1 kHz, which is phase modulated by the ATIP
signal.
7.17.3 THE ATIP BIT DETECTOR
This function extracts the ATIP information bits from the
ADC output and passes them to the ATIP read interface
block. It also outputs the ATIPSync pulse. In order to
protect the ATIPSyncs, a flywheel mechanism exists to
interpolate ATIPSyncs if none are detected. This is a
requirement to ensure that the recording process does not
get corrupted.
7.17.4 THE ATIP READ INTERFACE
The ATIP data is read by the on-chip microprocessor. Data
availability can be checked by polling the ATIPReady bit in
the ATIP Status Register. The microprocessor must read
both the ATIPData and ATIPDataEnd registers in order to
complete the data read process correctly. If this does not
happen, a status bit is set to warn the microcontroller.
7.17.5 WOBBLE CONFIGURATION REGISTER 1 (WOBBLECONFIG1)
This is a dual-function register, the specific function is determined by the state of bit 7. When bit 7 = 0, the function is as
described in Tables 135 to 138. When bit 7 = 1, the function is as described in Tables 135 and 139.
Table 135 Wobble Configuration Register 1 (address 27H) - WRITE
7
6
5
4
3
2
1
0
0
0
PLLIntBW.2 PLLIntBW.1 PLLIntBW.0 LoopBW.2 LoopBW.1 LoopBW.0
1
ATIPhold
−
WinWidth.4 WinWidth.3 WindWidth.2 WindWidth.1 WindWidth.0
Table 136 Description of WobbleConfig1 bits, bit 7 = 0
BIT
5
4
3
2 to 0
SYMBOL
PLLIntBW.2
PLLIntBW.1
PLLIntBW.0
LoopBW<2:0>
DESCRIPTION
These 3 bits select the integrator bandwidth; see Table 137.
These 3 bits select the loop bandwidth; see Table 138. The PLL
bandwidth is proportional to the system clock frequency and determines
the following performance points:
• Loop bandwidth should be approximately equal to bit rate to get good
detector performance
• Loop bandwidth depends on ATIP signal scaling. Current figures are
valid for −6 dB scaling
• PLL lock-in range is approximately equal to loop bandwidth.
2000 Mar 21
59
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