SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.16.4 EFM CLOCK CONFIGURATION REGISTER 4
(EFMCLOCKCONF4)
This is a dual-function register, the specific function is
controlled by the state of bit 7.
The sample rate of the integrator may be programmed by
writing to this register when the MSB is set to a logic 1.
Higher sample rates let the integrator work faster. This is
effectively the same as increasing the Ki value.
Good stability and critical damping of the integrator can be
expected with a sample rate of 1/98 EFM frames and
Ki = 2-7 at n = 2.
The position error set-point may be programmed by writing
to this register when the MSB is set to a logic 0. A position
error setpoint between −64 and 63 can be programmed
using the remaining 7 bits.
On reset this register has the value −8.
Table 132 EFM Clock Configuration Register 4 (address 37H) - WRITE
7
6
5
4
3
1
−
−
−
−
0
PosErr.6
PosErr.5 PosErr.4 PosErr.3
2
−
PosErr.2
1
0
Samplerate.1 Samplerate.0
PosErr.1
PosErr.0
Table 133 Selection of the integrator sample rate
Samplerate.1 Samplerate.0
0
0
392
0
1
196
1
0
98
1
1
49
SAMPLE RATE
Table 134 EFMPLL settings information
INTENDED
ENCODER SPEED
n=1
n=2
n=4
DIGITAL
MULTIPLICATION
FACTOR
294
147
98
ANALOG PLL
MULTIPLICATION
FACTOR
4
4
4
PROGRAMMABLE POSITION ERROR
DIVIDER FACTOR TIME CONSTANT
12
2581 ms
6
635 ms
4
160 ms
2000 Mar 21
58
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