SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.16.1 EFM CLOCK CONFIGURATION REGISTER 1 (EFMCLOCKCONF1)
Table 120 EFM Clock Configuration Register 1 (address 34H) - WRITE
7
6
5
4
3
2
1
0
DPLLBW.2 DPLLBW.1 DPLLBW.0 Bypass
Div.2
Div.1
Div.0
−
Table 121 Description of EFMClockConf1 bits
BIT
SYMBOL
DESCRIPTION
7
DPLLBW.2 These 3 bits select the digital PLL bandwidth; see Table 122.
6
DPLLBW.1
5
DPLLBW.0
4
Bypass
When Bypass = 0, then bypass is off. When Bypass = 1, then PLL is bypassed and the
XEFM clock is derived from the system clock.
3
Div.2
These 3 bits select the analog PLL output divisor; see Table 123.
2
Div.1
1
Div.0
0
−
This bit is reserved.
Table 122 Selection of PLL bandwidth
DPLLBW.2
0
0
0
0
1
DPLLBW.1
0
0
1
1
0
DPLLBW.0
PLL BANDWIDTH
0
Digital PLL bandwidth is 400 Hz.
1
Digital PLL bandwidth is 200 Hz.
0
Digital PLL bandwidth is 100 Hz.
1
Digital PLL bandwidth is 50 Hz.
0
Digital PLL bandwidth is 25 Hz.
Table 123 Selection of analog PLL output divisor
Div.2
0
0
0
0
1
1
1
1
Div.1
0
0
1
1
0
0
1
1
Div.0
0
1
0
1
0
1
0
1
PLL DIVISOR
Analog PLL output is divided by 1 (XEFM_2 output is not available).
Analog PLL output is divided by 2.
Analog PLL output is divided by 3 (XEFM_2 output is not available).
Analog PLL output is divided by 4.
Analog PLL output is divided by 6.
Analog PLL output is divided by 8.
Analog PLL output is divided by 12.
Analog PLL output is divided by 16.
2000 Mar 21
55
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