SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
Table 137 Selection of integrator bandwidth
PLLIntBW.2 PLLIntBW.1 PLLIntBW.0
INTEGRATOR BANDWIDTH
0
0
0
1.32 kHz for 4.26 MHz system clock
0
0
1
662 Hz for 4.26 MHz system clock
0
1
0
331 Hz for 4.26 MHz system clock
0
1
1
166 Hz for 4.26 MHz system clock
1
0
0
83 Hz for 4.26 MHz system clock
1
0
1
42 Hz for 4.26 MHz system clock
1
1
0
21 Hz for 4.26 MHz system clock
1
1
1
10 Hz for 4.26 MHz system clock
Table 138 Selection of loop bandwidth
LOOPBW.2
0
0
0
0
1
1
1
1
LOOPBW.1
0
0
1
1
0
0
1
1
LOOPBW.0
LOOP BANDWIDTH
0
10.6 kHz for 4.26 MHz system clock
1
5.3 kHz for 4.26 MHz system clock
0
2.65 kHz for 4.26 MHz system clock
1
1.32 kHz for 4.26 MHz system clock
0
662 Hz for 4.26 MHz system clock
1
331 Hz for 4.26 MHz system clock
0
166 Hz for 4.26 MHz system clock
1
83 Hz for 4.26 MHz system clock
Table 139 Description of WobbleConfig1 bits, bit 7 = 1
BIT
SYMBOL
DESCRIPTION
6
ATIPhold When ATIPhold = 1, then Wobble PLL in Hold mode.
5
−
This bit is reserved.
4
WinWidth.4 Determines the half of the width of the window where ATIP syncs are being accepted for
3
WinWidth.3 resynchronization. The unit of WindowWidth is ATIP clock pulses. As an ATIP frame
2
WinWidth.2
consists of 42 ATIP clock pulses, the maximum value of WindowWidth that can be
programmed is 21. The reset value is logic 0. The OutOfWindow state can be detected
1
WinWidth.1 by reading the ATIPStatus register.
0
WinWidth.0
2000 Mar 21
60
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