VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Current state CS RAS CA WE Address
Command
Action
(3/3)
Notes
Write
H X X XX
recovering
L
H
H HX
DESL
NOP
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
L H H LX
BST
Nop → Enter row active after tDPL
L
H
L H BA, CA, A10 READ/READA Start read, Determine AP
8
L
H
L
L BA, CA, A10 WRIT/WRITA New write, Determine AP
L
L
H H BA, RA
ACT
ILLEGAL
3
L
L H L BA, A10
PRE/PALL
ILLEGAL
3
L
L
L HX
PEF/SELF
ILLEGAL
L
L
L L Op - Code MRS
ILLEGAL
Write
H X X XX
recovering
with auto
L
H
H HX
precharge
L H H LX
DESL
NOP
BST
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
L
H
L H BA, CA, A10 READ/READA ILLEGAL
3,8
L
H
L
L BA, CA, A10 WRIT/WRITA ILLEGAL
3
L
L
H H BA, RA
ACT
ILLEGAL
3
L
L
H L BA, A10
REF/PALL
ILLEGAL
3
L
L
L HX
REF/SELF
ILLEGAL
L
L
L
L Op - Code MRS
ILLEGAL
Auto
H X X XX
Refreshing
L
H
H XX
L
H
L
XX
DESL
NOP/BST
READ/WRIT
Nop Enter idle after tRC
Nop Enter idle after tRC
ILLEGAL
L
L
H XX
ACT/PRE/PALL ILLEGAL
L
L
L XX
Mode regis- H X X X X
ter setting
L H H HX
REF/SELF/MRS ILLEGAL
DESL
Nop → Enter idle after 2 Clocks
NOP
Nop → Enter idle after 2 Clocks
L H H LX
BST
ILLEGAL
L
H
L
XX
READ/WRITE ILLEGAL
L
L
X XX
ACT/PRE/
PALL/
ILLEGAL
Note 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which dont’ satisfy t DPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but for multibanks interleave
Document : 1G5-0154
Rev.1
Page 12
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