VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
7.Precharge
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
The precharge command can be asserted anytime after tRAS(min) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM
enters the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is
as follows.
PrechargeE
CLK
Command
CAS latency = 2
DQ
Burst lengh=4
T0
T1
T2
T3
T4
T5
T6
T7
Read
PRE
Q0
Q1
Q2
Q3
Hi - Z
Command
Read
CAS latency = 3
DQ
Q0
CAS latency = 2 : One clock earlier than the last output data.
3 : Two clocks earlier than the last output data.
PRE
Hi - Z
Q1
Q2
Q3
(tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter ”t DPL” must be satis-
fied. The tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The
minimum number of clocks can be calculated by dividing tDPL(min.) by the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the
last data word is valid. In the following table, minus means clocks before the reference; plus means time
after the reference.
CAS latency
2
3
Read
-1
-2
Write
+ tDPL(min.)
+ tDPL(min.)
Document : 1G5-0154
Rev.1
Page 17
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