VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
8.3 Multibank Operation- Read with Auto Precharge
During a READA cycle interrupted by a Read, Write command of another banks, the auto-pre-
charge scheduled time would not be changed.
Multibank Operation
Burst lengh=8
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14
CLK
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
READA A
READA A
Read B
Auto precharge bank A starts
QA0 QA1 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7
Hi-Z
Auto precharge bank A starts
Read B
QA0 QA1 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7
Hi-Z
Similiar top.21
Document : 1G5-0154
Rev.1
Page 20
Share Link: 
