VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
8.Auto Precharge
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high
in the read or write command (Read with Auto precharge command or Write with Auto precharge com-
mand), auto precharge is selected and begins automatically after the burst access.
In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank
being precharged.
When using auto precharge in the read cycle, knowing when the precharge starts is important because
the next activate command to the bank being precharged cannot be executed until the precharge cycle
ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has
been satisfied.
A Read or Write command without auto - precharge can be terminated in the midst of a burst operation.
However, a Read or Write command with auto - precharge can not be interrupted by the same bank com-
mands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Pre-
charge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be
noted that the device will not respond to the Auto - Precharge command if the device is programmed for full
page burst read or write cycles.
The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed
into the mode register and whether the cycle is read or write.
8.1 Read with Auto Precharge
During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier
(CL = 3) than the last word output.
READ with AUTO PRECHARGE
Burst lengh = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
CAS latency = 2
READA B
No New Command to Bank B
Auto precharge starts
DQ
Command
READA B
QB0
QB1
QB2
QB3
No New Command to Bank B
Auto precharge starts
CAS latency = 3
DQ
QB0
QB1
QB2
Remark READA means READ with AUTO PRECHARGE
Hi - Z
QB3 Hi - Z
Document : 1G5-0154
Rev.1
Page 18
Share Link: 
