VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE Note 1
Current state
CKE RAS CS RAS CAS WE
n-1 n
Address
Action
Self refresh
(S.R.)
H
X
X
X
X
X
L
H
H
X
X
X
X INVALID, CLK (n-1)would exit S.R.
X S.R. Recovery
L
H
L
H
H
X
X S.R. Recovery
L
H
L
H
L
X
X ILLEGAL
LHL
L
X
X
X ILLEGAL
L
L
X
X
X
X
X Maintain S.R.
Self refresh
recovery
H
H
H
X
X
X
HH
L
H
H
X
X
Idle after tRC
X
Idle after tRC
HH
L
H
L
X
X ILLEGAL
HHL
L
X
X
X ILLEGAL
H
L
H
X
X
X
X Begin clock suspend next cycle
H
L
L
H
H
X
X Begin clock suspend next cycle
H
L
L
H
L
X
X ILLEGAL
HL
L
L
X
X
X ILLEGAL
L
H
X
X
X
X
X Exit clock suspend next cycle
L
L
X
X
X
X
X Maintain clock suspend
Power down
(P.D.)
H
X
X
X
X
X
L
H
X
X
X
X
INVALID, CLK(n-1) would exit P.D.
X
EXIT P.D.→ Idle
L
L
X
X
X
X
X Maintain power down mode
Both banks idle H H H X X X
Refer to operations in Operative
Command Table
HH
L
H
X
X
Refer to operations in Operative
Command Table
HHL
L
HX
Refer to operations in Operative
Command Table
HHL
L
L
H
X Auto Refresh
HHL
L
L
L Op-Code Refer to operations in Operative
Command Table
H
L
H
X
X
X
Refer to operations in Operative
Command Table
H
L
L
H
X
X
Refer to operations in Operative
Command Table
HL
L
L
HX
Refer to operations in Operative
Command Table
HL
L
L
L
H
X Self refresh
HL
L
L
L
L Op-Code Refer to operations in Operative
Command Table
Notes
2
2
5
5
2
2
3
L
X
X
X
X
X
X Power down
3
Any state other H H X X X X
than listed above
X Refer to operations in Operative
Command Table
H
L
X
X
X
X
X Begin clock suspend next cycle
4
L
H
X
X
X
X
X Exit clock suspend next cycle
L
L
X
X
X
X
X Maintain clock suspend
Note 1. H : Hight level, L : low level, X : High or low level (Don't care)
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time
must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. IIIegal if tSREX is not satisfied.
Document : 1G5-0154
Rev.1
Page 13
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