VG36128401A View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG36128401A' PDF : 69 Pages View PDF
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
8.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.)
after the last data word input to the device.
WRITE with AUTO PRECHRGE
T0
T1
T2
T3
T4
T5
T6
CLK
Command
CAS latency = 2
WRITA B
No New Command to Bank B
AUTO PRECHARGE starts
tDPL
DQ
Command
CAS latency = 3
DQ
DB0
WRITA B
DB1
DB2
DB3
No New Command to Bank B
AUTO PRECHARGE starts
tDPL
DB0
DB1
DB2
DB3
Remark WRITA means WRITE with AUTO Precharge
Burst lengh = 4
T7
T8
Hi - Z_
Hi - Z
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data
word is valid.
In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency
2
3
Read
-1
-2
Write
+ tDPL(min.)
+ tDPL(min.)
Document : 1G5-0154
Rev.1
Page 19
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